Design and Analysis of Transient Fault Tolerance for Multi Core Architecture

This paper describes the software approach of fault tolerance for shared memory multi core system using PLR.PLR uses a software-centric approach transient fault tolerance which ensuring a correct software execution. This scheme is used at user space level which does not necessitate changes to the original application.PLR create a set of redundant process per application process. In this scheme multithread redundant process is mainly used to detect the soft errors and recover from the fault. The main goal is to use software leverage by available using hardware parallelism for low overhead fault tolerance. Fault tolerance which allow the system perform correctly even in the presence of faults. In existed the system is appraised for fault coverage performance. This paper presents Software based multi core alternatives for design and analysis transient fault tolerance using process-level redundancy (PLR) which implements fault error detection and fault recovery. This is flexible alternative but higher overhead correctness is defined by software output overhead incurred by our approach ranges is lower when comparable to existed. It furnishes a low overhead mechanism and render improved performance over existent software transient fault tolerance techniques. Index terms -Fault tolerance, transient faults, soft errors, process-level redundancy.